一个4位计数器程序在ISE 联合modelsim进行仿真,代码如下

testbench的内容:

module count4_tb;

reg clk,reset;
wire [3:0] out;
parameter DELY=100;

count4 mycount(out,reset,clk);

always #(DELY/2) clk=~clk;

initial begin
clk=0;
reset=0;
#DELY reset=1;
#DELY reset=0;
#(DELY*200) $finish;
end

initial $monitor($time,,,"clk=%d reset=%d out=%d",clk,reset,out);

endmodule

count4.v的内容:

module count4(out,reset,clk
);

output [3:0] out;
input reset,clk;
reg [3:0] out;

always@(posedge clk) begin
if(reset)
out<=0;
else
out<=out+1;
end

endmodule

功能仿真,没有错误,而布局布线后仿真,有如下错误提示

改正办法:

将testbench 中的 count4 mycount(out,reset,clk);改为count4 mycount(.out(out),.reset(reset),.clk(clk));时序仿真就会正确运行。